Methods of Driving Nonvolatile Memory Devices that Utilize Read/Write Merge Circuits

ABSTRACT

An integrated circuit memory device includes an array of nonvolatile memory cells (e.g., variable resistance cells) having a first plurality of lines electrically coupled to memory cells therein. A read/write control circuit is provided. The read/write control circuit includes a read/write merge circuit and a column selection circuit. The read/write control circuit, which is configured to drive a selected one of the first plurality of lines with unequal write and read voltages during respective write and read operations, includes a compensating unit. This compensating unit is configured to provide a read compensation current to the selected one of the first plurality of lines circuit during the read operation.

REFERENCE TO PRIORITY APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.11/945,443, now U.S. Pat. No. ______, which claims the benefit of KoreanApplication No. 2006-131242, filed Dec. 20, 2006, the disclosures ofwhich are hereby incorporated herein by reference.

FIELD OF THE INVENTION

The present invention relates to nonvolatile memory devices and methodsof operating same and, more particularly, to nonvolatile memory devicesand methods of operating the same.

BACKGROUND OF THE INVENTION

Some examples of nonvolatile memory devices using resistance materialsinclude resistive random access memory (RRAM) devices, phase-changeablerandom access memory (PRAM) devices and magnetic random access memory(MRAM) devices. Dynamic random access memory (DRAM) devices or flashmemory devices store data by using charges, while nonvolatile memorydevices use resistance materials to store data using a change inresistance of a variable resistance material (RRAM), a state change of aphase change material like a chalcogenide alloy (PRAM) or a change inresistance of a magnetic tunnel junction (MTJ) thin film according tothe magnetization of a ferromagnetic material (MRAM), for example.

Here, resistive memory cells include variable resistance materialsbetween an upper electrode and a lower electrode, and a resistance levelof the variable resistance materials changes according to a voltage thatis applied to the upper and lower electrodes. Examples of such resistivememory cells are disclosed in U.S. Patent Publication No. 2005/0058009and U.S. Patent Publication No. 2004/0027849. In particular, a filamentthat serves as a current path of a cell current is formed in thevariable resistance material. A state in which a part of the filament isdisconnected may be defined as a reset state, a high-resistance state,and reset data (data 1). A state in which the filament is connected maybe defined as a set state, a low-resistance state, and set data (data0).

A reset voltage that has a voltage level at which the filament may bedisconnected is supplied to write reset data into the resistive memorycells. A set voltage that has a voltage level at which the filament maybe reconnected is supplied to write set data into the resistive memorycells. Further, a voltage that has a voltage level that is too low tochange the state of the filament is supplied to read the stored data tofind out whether the read data is reset data or set data.

SUMMARY OF THE INVENTION

An integrated circuit memory device according to an embodiment of theinvention includes an array of nonvolatile memory cells having a firstplurality of lines electrically coupled to memory cells therein. Thenonvolatile memory cells may be variable-resistance memory cells and thefirst plurality of lines may be bit lines. A read/write control circuitis also provided. The read/write control circuit is configured to drivea selected one of the first plurality of lines with unequal write andread voltages during respective write and read operations. Theread/write control circuit includes a compensating unit configured toprovide a read compensation current to the selected one of the firstplurality of lines during the read operation. This compensating unit isdisabled during the write operation.

According to additional embodiments of the invention, the read/writecontrol circuit may also include a line controller, which is configuredto regulate the selected one of the first plurality of bit lines at theread voltage during the read operation and regulate the selected one ofthe first plurality of bit lines at the write voltage during the writeoperation. This regulation may be performed using a comparator having afirst input terminal electrically coupled to a sensing node (NS) in theread/write control circuit, which is driven with the compensatingcurrent during the read operation. The read/write control circuit mayfurther include a precharge unit configured to drive the sensing nodewith a precharge current during a portion of the read operation and adischarge unit configured to discharge the sensing node in preparationfor a read operation.

Still further embodiments of the invention include sensing a readvoltage on a bit line electrically connected to a variable-resistancememory cell during an operation to read a state of the memory cell whilesimultaneously supplying a read compensating current to the bit line.The magnitude of the read compensating current is sufficient to boost avoltage on the bit line when the memory cell is in a relatively highresistance state, but insufficient to appreciably boost a voltage on thebit line when the memory cell is in a relatively low resistance state.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of the present inventionwill become more apparent by describing in detail preferred embodimentsthereof with reference to the attached drawings in which:

FIG. 1 is a block diagram illustrating a nonvolatile memory deviceaccording to an embodiment of the invention;

FIG. 2 is a block diagram illustrating a read/write merge circuit thatis used for a nonvolatile memory device according to an embodiment ofthe present invention;

FIG. 3 is a block diagram illustrating a bit line level controller ofFIG. 2 in more detail;

FIG. 4 is an exemplary circuit diagram illustrating a read/write mergecircuit of FIGS. 2 and 3;

FIG. 5 is a timing diagram illustrating a write operation and a readoperation of a nonvolatile memory device according to an embodiment ofthe present invention; and

FIG. 6 is a block diagram illustrating a nonvolatile memory deviceaccording to another embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Advantages and features of the present invention and methods ofaccomplishing the same may be understood more readily by reference tothe following detailed description of preferred embodiments and theaccompanying drawings. The present invention may, however, be embodiedin many different forms and should not be construed as being limited tothe embodiments set forth herein. Rather, these embodiments are providedso that this disclosure will be thorough and complete and will fullyconvey the scope of the invention to those skilled in the art. Likereference numerals refer to like elements throughout the specification.

It will be understood that when an element is referred to as being“connected to” or “coupled to” another element, it can be connected orcoupled to the other element or intervening elements may be present. Incontrast, when an element is referred to as being “directly connectedto” or “directly coupled to” another element, there are no interveningelements present. As used herein, the term “and/or” includes any and allcombinations of one or more of the associated listed items.

It will be understood that, although the terms first, second, etc. maybe used herein to describe various elements, components, and/orsections, these elements, components, and/or sections should not belimited by these terms. These terms are only used to distinguish oneelement, component or section from another element, component, orsection. Thus, a first element, component, or section discussed belowcould be termed a second element, component, or section withoutdeparting from the teachings of the present invention.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising,” when used in this specification, specify thepresence of stated components, steps, operations, and/or elements, butdo not preclude the presence or addition of one or more othercomponents, steps, operations, and/or elements.

In addition, when terms used in this specification are not specificallydefined, all the terms used in this specification (including technicaland scientific terms) can be understood by those skilled in the art.Further, when general terms defined in the dictionaries are notspecifically defined, the terms will have the normal meaning in the art.

The present invention will now be described more fully with reference tothe accompanying drawings, in which preferred embodiments of theinvention are shown.

Hereinafter, a description will be made of embodiments of the presentinvention by using resistive random access memory (RRAM) devices.However, it will be understood by those skilled in the art that thepresent invention can be applied to nonvolatile memory devices, such asphase-changeable random access memory (PRAM) devices, magnetic RAM(MRAM) devices, and the like, which use resistance materials.

FIG. 1 is a block diagram illustrating a nonvolatile memory deviceaccording to an embodiment of the present invention. The nonvolatilememory device shown in FIG. 1 may be, for example, a uni-directionalresistive memory device, but is not limited thereto. Referring to FIG.1, the nonvolatile memory device according to the embodiment of thepresent invention includes a memory cell array 1, a row selectioncircuit 60, a column selection circuit 50, and a read/write mergecircuit 10. The memory cell array 1 may include a plurality of bit linesBL, a plurality of word lines WL, and a plurality of nonvolatile memorycells 70. Each of the nonvolatile memory cells 70 is coupled to acorresponding one of the bit lines BL and a corresponding one of theword lines WL. Each of the nonvolatile memory cells 70 may include avariable resistive element Rc, which has a different resistance levelaccording to stored data, and an access element Acl that controls a cellcurrent flowing through the variable resistive element Rc. A filamentthat serves as a current path for the cell current may be formed insidethe variable resistive element Rc. A state in which a part of thefilament is disconnected is defined as a reset state, and a state inwhich the filament is fully connected is defined as a set state. Thevariable resistive element may be formed of a material such as NiO.Here, the access element Acl is shown as an FET transistor, but theaccess element may be another type of switching device. For example, adiode, a PNP bipolar transistor, an NPN bipolar transistor, and similarswitching devices may be used as the access element Acl.

The row selection circuit 60 and the column selection circuit 50designate a row and a column of a nonvolatile memory cell, respectively,so that a nonvolatile memory cell 70 may be selected from a plurality ofother nonvolatile memory cells 70 in the memory cell array 1. Theread/write merge circuit 10 and the column selection circuit 50 arecollectively referred to herein and in the claims as a read/writecontrol circuit.

The read/write merge circuit 10 performs read/write operations in theselected nonvolatile memory cell 70. That is, the read/write mergecircuit 10 supplies a reset voltage VRESET, which has a voltage level atwhich the filament may be disconnected, and writes reset data into thenonvolatile memory cell. The read/write merge circuit 10 may also supplya set voltage VSET, which has a voltage level at which the filament maybe reconnected, and thereby write set data into the nonvolatile memorycell. Moreover, the read/write merge circuit 10 can supply a clampvoltage that has a voltage level too low to change a state of thefilament and thereby read stored data to find out whether the data isreset data or set data. Here, the set voltage VSET has a higher voltagelevel than the reset voltage VRESET, and a clamp voltage VRD (i.e., aclamped read voltage) has a lower voltage level than the reset voltageVRESET.

In particular, in the nonvolatile memory device according to theembodiment of the present invention, a circuit that performs a writeoperation and a circuit that performs a read operation are merged.Specifically, a circuit that supplies the reset voltage VRESET and theset voltage VSET to the bit line BL that is coupled to the nonvolatilememory cell 70 during a write operation, and a circuit that clamps thebit line BL during a read operation are merged. This will be describedin detail with reference to FIGS. 2 to 5.

In the embodiment of FIG. 1, the read/write merge circuit 10 is coupledto the bit line BL so as to write data into the nonvolatile memory cell70 or read the data from the nonvolatile memory cell 70, but the presentinvention is not limited to this configuration. For example, theread/write merge circuit 10 may be coupled to the word line WL inalternative embodiments of the invention.

FIG. 2 is a block diagram illustrating a read/write merge circuit 10that is used in a nonvolatile memory device according to an embodimentof the invention. FIG. 3 is a block diagram illustrating the bit linelevel controller of FIG. 2.

First, referring to FIGS. 2 to 4, the nonvolatile memory deviceaccording to the embodiment of the present invention includes theread/write merge circuit 10, the column selection circuit 50, the rowselection circuit 60, and the nonvolatile memory cell 70. Specifically,the column selection circuit 50 receives a column selection signal YSELand selects a bit line BL, and the row selection circuit 60 receives arow selection signal XSEL and selects a word line WL, such that thenonvolatile memory cell 70 on which a write or read operation isperformed is selected. The read/write merge circuit 10 can perform botha write operation and a read operation. The read/write merge circuit 10includes a precharge unit 12, a compensating unit 14, a discharge unit16, a sense amplifier 18, and a bit line level controller 20.

The precharge unit 12 precharges the bit line BL to a predeterminedlevel, for example, a power supply voltage VDD, through a sensing nodeNS before a sensing operation is performed by the sense amplifier 18. Asshown in FIG. 4, the precharge unit 12 may include a PMOS transistor MP1that is serially coupled between a power supply voltage terminal VDD andthe sensing node NS and has a gate to which a write enable signal WE isapplied, and a transistor MP2 that has a gate to which a prechargecontrol signal VPRE is applied.

When the read operation starts, the discharge unit 16 discharges the bitline BL to a predetermined level, for example, a ground voltage VSS,through the sensing node NS before the precharge operation is performedby the precharge unit 12. Specifically, in the nonvolatile memory deviceaccording to the embodiment of the present invention, the reset voltageand the set voltage are supplied to the selected nonvolatile memory cell70 through the sensing node NS that is coupled to the bit line BL so asto write the data. The data in the selected nonvolatile memory cell 70is also read through the sensing node NS. Therefore, when the readoperation is performed right after the write operation, a voltage levelof the sensing node NS, which is increased by the reset voltage or theset voltage during the write operation, may affect the read operation.Therefore, in order to prevent this, when the read operation starts, thevoltage level of the sensing node NS is first discharged. As shown inFIG. 4, the discharge unit 16 may include an NMOS transistor MN1 that iscoupled between the sensing node NS and the ground voltage terminal VSSand has a gate to which a discharge control signal PDIS is applied.

The compensating unit 14 is enabled after the precharge unit 12 performsa precharge operation. The compensation unit 14 serves to supply acompensating current to the bit line BL through the sensing node NS inorder to compensate for a decrease in the voltage level of the bit lineBL that occurs when a cell current Icell flows through the selectednonvolatile memory cell 70. Specifically, when the nonvolatile memorycell 70 is in a set state, since resistance of the variable resistiveelement Rc is small, the amount of cell current Icell is relativelylarge. When the nonvolatile memory cell 70 is in a reset state, sinceresistance of the variable resistive element Rc is large, the amount ofcell current Icell is relatively small. Here, the compensating unit 14may supply the compensating current so that the cell current Icell inthe reset state is compensated. In this way, the level of the sensingnode NS remains approximately constant in the reset state, while thelevel of the sensing node NS decreases in the set state. Therefore,there will be a significant difference between the level of the sensingnode NS in the reset state and the level of the sensing node NS in theset state, and thus it is relatively easy to differentiate the set statefrom the reset state. In this way, a sensing margin can be increased. Asshown in FIG. 4, the compensating unit 14 may include a PMOS transistorMP3 that is serially coupled between the power supply voltage terminalVDD and the sensing node NS and has a gate to which a write enablesignal WE is applied, and a PMOS transistor MP4 that has a gate to whicha compensation control signal VBIAS is applied.

The sense amplifier 18 compares the level of the sensing node NS with areference level REF and outputs a comparison result. According to theembodiment of the present invention, the sense amplifier 18 may be acurrent sense amplifier, which senses a change in the current flowingout through the bit line BL of the selected nonvolatile memory cell 70with respect to the reference current, or a voltage sense amplifier,which senses a change in voltage with respect to a reference voltage.

During a read operation, the bit line level controller 20 supplies aclamp voltage VRD to the bit line BL and clamps the bit line BL withinan appropriate level so as to read data of the bit line BL (i.e., withina predetermined level below a threshold voltage Vth of the variableresistive element). Further, during a write operation, the bit linelevel controller 20 supplies a write voltage VWT (i.e., reset voltageVRESET or set voltage VSET) to the bit line BL and writes data into thenonvolatile memory cell. Here, the reason why the bit line BL is clampedduring a read operation is that when the variable resistive element isapplied with a voltage larger than the threshold voltage Vth, data maybe written into the variable resistive element of the selectednonvolatile memory cell 70. Thus, according to this embodiment of theinvention, VRD<VRESET<VSET.

The bit line level controller 20 includes a comparing unit 22, a voltagesupplying unit 24, a write voltage supplying unit 26, and a clampvoltage supplying unit 28. The comparing unit 22 receives a voltagelevel of the sensing node NS to be fed back, compares a voltage level ofthe write voltage VWT (i.e., reset voltage VRESET or set voltage VSET),which is supplied from the write voltage supplying unit 26, with thevoltage level of the sensing node NS during the write operation, andsupplies a comparison result COMP. During the read operation, thecomparing unit 22 compares a voltage level of the clamp voltage VRD,which is supplied from the clamp voltage supplying unit 28, with thevoltage level of the sensing node NS, and supplies a comparison resultCOMP. Here, the set voltage VSET has a higher level than the resetvoltage VRESET, and the clamp voltage VRD has a lower voltage level thanthe reset voltage VRESET.

The voltage supplying unit 24 regulates the voltage level of the sensingnode NS to the level of the write voltage VWT (i.e. voltage level of thereset voltage VRESET or the set voltage VSET) according to thecomparison result COMP during the write operation. Further, the voltagesupplying unit 24 regulates the voltage level of the sensing node NS tothe voltage level of the clamp voltage VRD according to the comparisonresult COMP during the read operation.

The write voltage supplying unit 26 may be a PMOS transistor MP6 that iscoupled between the write voltage terminal VWT and a node NA and has agate to which a complementary signal WEB of the write enable signal WEis applied. The clamp voltage supplying unit 28 may be a PMOS transistorMP7 that is coupled between the clamp voltage terminal VRD and the nodeNA and has a gate to which the write enable signal WE is applied. Thecomparing unit 22 may be a unit gain amplifier that compares a voltageof the sensing node NS with a voltage of the node NA and outputs acomparison result COMP. The voltage supplying unit 24 may be a PMOStransistor MP5 that is coupled between an external power supply voltageterminal VEXT and the sensing node NS and has a gate to which thecomparison result COMP is applied.

Accordingly, because the bit line level controller 20 used in thenonvolatile memory device according to embodiments of the presentinvention receives a voltage level of the sensing node NS to be fed backand controls the voltage level of the sensing node NS in response, avoltage level of the bit line BL or the sensing node NS can beaccurately controlled to a desired voltage level, thereby increasing thereliability of the read/write operations. That is, the bit line levelcontroller 20 can accurately control the voltage level of the bit lineBL to the voltage level of the reset voltage VRESET or the set voltageVSET during the write operation, or clamp the bit line BL during theread operation. In addition, since manufacturers or designers can easilycontrol the clamp voltage VRD and the write voltage VWT, for example,the voltage level at which the bit line BL is clamped during the readoperation can be easily controlled by controlling the clamp voltage VRD.In addition, since both the write voltage supplying unit 26 and theclamp voltage supplying unit 28 are coupled to one comparing unit 22,the size of the comparing unit 22 that is provided in a chip can beminimized.

Hereinafter, with reference to FIGS. 2, 3, and 5, a write operation anda read operation of a nonvolatile memory device according to anembodiment of the present invention will be described. FIG. 5 is atiming diagram illustrating a write operation and a read operation of anonvolatile memory device according to an embodiment of the presentinvention.

Since the complementary signal WEB of the write enable signal WE is at alow level, the write operation starts. The column selection signal YSELis synchronized with the input address XAi and becomes a high level,such that a bit line BL is selected. Then, the row selection signal XSELis synchronized with the column selection signal YSEL and becomes a highlevel, such that a word line WL is selected. In response to the activelow level of the complementary signal WEB of the write enable signal WE,the read/write merge circuit 10 supplies a write voltage VWT (i.e.,reset voltage VRESET or set voltage VSET) to the selected bit line BL,and writes the desired data into the selected nonvolatile memory cell.

During a read operation, the complementary signal WEB of the writeenable signal WE is set to a high level. The column selection signalYSEL is synchronized with the input address XAi and becomes a highlevel, and a bit line BL is selected. Then, the discharge control signalPDIS becomes a high level and discharges the bit line BL through thesensing node NS. When the read operation is performed right after thewrite operation, the voltage level of the sensing node NS, which isincreased by the reset voltage or the set voltage during the writeoperation, may affect the read operation. Therefore, in order to preventthis, the voltage level of the sensing node NS is discharged when theread operation starts.

After discharging the sensing node NS, the precharge control signal VPREbecomes a low level and precharges the bit line BL through the sensingnode NS. The row selection signal XSEL also becomes a high level and aword line WL is selected.

Because the complementary signal WEB of the write enable signal WE is ata high level, the read/write merge circuit 10 clamps a voltage level ofthe selected bit line BL within an appropriate level so as to read data.Specifically, the voltage level of the selected bit line BL is clampedwithin a predetermined level below the threshold voltage Vth of thevariable resistive element. The compensating unit 14 also supplies acompensating current to the sensing node NS so as to compensate for adecrease in the voltage level of the sensing node NS that occurs due tothe current Icell that flows through the selected nonvolatile memorycell 70. In such a state, the cell current Icell that depends on theresistance of the selected nonvolatile memory cell 70 is generated. Whenthe nonvolatile memory cell 70 is in a set state, since the resistanceof the variable resistive element is small, the amount of cell currentIcell is large. When the nonvolatile memory cell 70 is in a reset state,since the resistance of the variable resistive element is large, theamount of cell current Icell is small. However, since the compensatingunit 14 supplies a compensating current, the level of the sensing nodeNS does not decrease significantly in the reset state, but the level ofthe sensing node NS decreases appreciably in the set state. Therefore,the sense amplifier 18 senses a difference ΔH between the level of thesensing node NS and the reference level VREF in the reset state or adifference ΔL between the level of the sensing node NS and the referencelevel VREF in the set state.

FIG. 6 is a block diagram illustrating a nonvolatile memory deviceaccording to another embodiment of the present invention. Thenonvolatile memory device of FIG. 6 may be, for example, abi-directional memory device, but is not limited thereto. Like referencenumerals refer to like elements that are substantially identical tothose in FIG. 1. Detailed descriptions of the corresponding elementswill be omitted.

Referring to FIG. 6, a nonvolatile memory device according to anotherembodiment of the present invention includes a memory cell array 2, arow selection circuit 60, a column selection circuit 50, a firstread/write merge circuit 10, and a second read/write merge circuit 30.

Though not shown in detail in the drawing, the memory cell array 2includes a plurality of bit lines BL, a plurality of sense lines SL, anda plurality of nonvolatile memory cells 71. Each of the nonvolatilememory cells 71 is coupled to each of the bit lines BL and each of thesense lines SL. Here, each of the nonvolatile memory cells 71 mayinclude a variable resistive element Rc that has different resistancelevels according to data and an access element Ac2 that controls a cellcurrent flowing through the variable resistive element Rc. The variableresistive element Rc may include perovskites. The perovskites can be anynumber of compositions, including manganites (e.g.,Pr_(0.7)Ca_(0.3)MnO₃, Pr_(0.5)Ca_(0.5)MnO₃ other PCMOs, LCMOs, etc.),titanates (e.g., STO:Cr), zirconates (e.g., SZO:Cr, Ca₂Nb₂O₇:Cr, andTa₂O₅:Cr), and the like. The perovskites are taken as an example for thevariable resistive element Rc, but the variable resistive element Rc isnot limited thereto. The access element Ac2 may be composed of twodiodes that are disposed in different directions.

The first and second read/write merge circuits 10 and 30 perform writeand read operations in a selected nonvolatile memory cell 70. The firstread/write merge circuit 10 writes set data by supplying a set voltageVSET to the selected nonvolatile memory cell 70. The second read/writemerge circuit 10 writes reset data by supplying a reset voltage VRESETto the selected nonvolatile memory cell 70. As the description has beenmade referring to FIGS. 2 and 3, each of the first and second read/writemerge circuits 10 and 30 may include a precharge unit 12, a compensatingunit 14, a discharge unit 16, and a sense amplifier 18, and a bit linelevel controller 20, as illustrated by FIGS. 2-4.

Although the present invention has been described in connection with theexemplary embodiments of the present invention, it will be apparent tothose skilled in the art that various modifications and changes may bemade thereto without departing from the scope and spirit of theinvention. Therefore, it should be understood that the above embodimentsare not limitative, but illustrative in all aspects.

1. A method of driving a nonvolatile memory device, the methodcomprising: preparing a nonvolatile memory device having a plurality ofnonvolatile memory cells correspondingly coupled to first lines andsecond lines, and a sensing node coupled to the first lines; supplying awrite voltage to the nonvolatile memory cells through the sensing nodeso as to write data; discharging the sensing node; precharging thesensing node; clamping the sensing node to a clamp voltage level; andsensing a change in the voltage level of the sensing node and readingdata stored in the nonvolatile memory cell while applying a compensatingcurrent to the sensing node.
 2. The method of claim 1, wherein the writevoltage includes a set voltage for writing set data into the nonvolatilememory cell and a reset voltage for writing reset data into thenonvolatile memory cell, and the set voltage has a higher voltage levelthan the reset voltage.
 3. The method of claim 2, wherein the clampvoltage has a lower voltage level than the reset voltage.
 4. A method ofoperating a nonvolatile memory device, comprising: programming a firstnonvolatile memory cell in the nonvolatile memory device by electricallycoupling a sensing node held at a first write voltage to a first bitline electrically coupled to the first nonvolatile memory cell; andreading a state of the first nonvolatile memory cell by: discharging thesensing node to a discharged voltage level; then precharging the sensingnode from the discharged voltage level to a first read voltage level;and then sensing a change in voltage of the sensing node from the firstread voltage level by electrically coupling the sensing node to thefirst bit line while concurrently supplying the sensing node with acompensating current.
 5. The method of claim 4, wherein the compensatingcurrent has a magnitude sufficient to hold the sensing node at about thefirst read voltage level when the first nonvolatile cell is programmedinto a first state, but insufficient to prevent a voltage of the sensingnode from dropping below the first read voltage level when the firstnonvolatile memory cell is programmed into a second state.
 6. The methodof claim 5, wherein the first state is a reset state and the secondstate is a set state.
 7. The method of claim 5, wherein said sensingcomprises supplying compensating current through a PMOS transistor. 8.The method of claim 4, wherein said sensing comprises comparing avoltage of the sensing node to a reference voltage; and wherein thecompensating current has a magnitude sufficient to hold the sensing nodeabove the reference voltage level when the first nonvolatile cell isprogrammed into a first state, but insufficient to prevent a voltage ofthe sensing node from dropping below the reference voltage when thefirst nonvolatile memory cell is programmed into a second state.
 9. Themethod of claim 4, wherein said programming comprises supplying a set orreset voltage to a first terminal of a comparator concurrently withfeeding back a voltage of the sensing node to a second terminal of thecomparator.
 10. A method of operating a nonvolatile memory device,comprising: programming a first uni-directional resistive memory cell inthe nonvolatile memory device into one of a set state and a reset state;and reading a state of the first uni-directional resistive memory cellby sensing a change in voltage of a sensing node electrically coupledthereto relative to a reference voltage, said reading comprisingsupplying the sensing node with a positive compensating current having amagnitude sufficient to hold the sensing node at a voltage greater thanthe reference voltage when the first uni-directional resistive memorycell is in the reset state, but insufficient to prevent a voltage of thesensing node from being pulled below the reference voltage when thefirst uni-directional resistive memory cell is in the set state andsinking current from the sensing node.
 11. The method of claim 10,wherein said reading comprises supplying the compensating currentthrough a PMOS transistor.
 12. The method of claim 10, wherein saidprogramming comprises supplying a set or reset voltage to a firstterminal of a comparator concurrently with feeding back a voltage of thesensing node to a second terminal of the comparator.
 13. The method ofclaim 10, wherein said reading further comprises sequentiallydischarging and then precharging the sensing node in advance ofsupplying the sensing node with the compensating current.